AN 954: Hierarchical Partial Reconfiguration Tutorial: for the Intel® Agilex® F-Series FPGA Development Board

ID 683687
Date 8/04/2021

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Step 6: Creating Revisions

The PR design flow uses the project revisions feature in the Intel® Quartus® Prime software. Your initial design is the base revision, where you define the static region boundaries and reconfigurable regions on the FPGA.

From the base revision, you create multiple revisions. These revisions contain the different implementations for the PR regions. However, all PR implementation revisions use the same top-level placement and routing results from the base revision.

To compile a PR design, you must create a PR implementation revision for each persona. In addition, you must specify the Partial Reconfiguration - Base or Partial Reconfiguration - Persona Implementation revision type for each of the revisions.

The following table lists the revision name and type for each revision you create:

Table 3.  Revision Names and Types
Revision Name Revision Type
blinking_led.qsf Partial Reconfiguration - Base
hpr_child_default.qsf Partial Reconfiguration - Persona Implementation
hpr_child_slow.qsf Partial Reconfiguration - Persona Implementation
hpr_child_empty.qsf Partial Reconfiguration - Persona Implementation
hpr_parent_slow_child_default.qsf Partial Reconfiguration - Persona Implementation
hpr_parent_slow_child_slow.qsf Partial Reconfiguration - Persona Implementation
Table 4.  Parent and Child Persona Revisions
Revision Name Parent Persona Behavior Child Persona Behavior
hpr_child_default.qsf Fast Blinking Fast Blinking
hpr_child_slow.qsf Fast Blinking Slow Blinking
hpr_child_empty.qsf Fast Blinking No Blinking (Always ON)
hpr_parent_slow_child_default.qsf Slow Blinking Fast Blinking
hpr_parent_slow_child_slow.qsf Slow Blinking Slow Blinking