AN 954: Hierarchical Partial Reconfiguration Tutorial: for the Intel® Agilex® F-Series FPGA Development Board
ID
683687
Date
8/04/2021
Public
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Step 1: Getting Started
Step 2: Creating a Child Level Submodule
Step 3: Creating Design Partitions
Step 4: Allocating Placement and Routing Region for PR Partitions
Step 5: Defining Personas
Step 6: Creating Revisions
Step 7: Compiling the Base Revision
Step 8: Preparing the PR Implementation Revisions for Parent PR Partition
Step 9: Preparing the PR Implementation Revisions for Child PR Partitions
Step 10: Programming the Board
Modifying an Existing Persona
Adding a New Persona to the Design
Step 1: Getting Started
To copy the reference design files to your working environment and compile the blinking_led flat design:
- Create a directory in your working environment, agilex_pcie_devkit_blinking_led_hpr.
- Copy the downloaded tutorials/agilex_pcie_devkit_blinking_led_hpr/flat sub-folder to the directory, agilex_pcie_devkit_blinking_led_hpr.
- In the Intel® Quartus® Prime Pro Edition software, click File > Open Project and select blinking_led.qpf.
- To elaborate the hierarchy of the flat design, click Processing > Start > Start Analysis & Synthesis. Alternatively, at the command-line, run the following command:
quartus_syn blinking_led -c blinking_led