AN 954: Hierarchical Partial Reconfiguration Tutorial: for the Intel® Agilex® F-Series FPGA Development Board

ID 683687
Date 8/04/2021

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Hierarchical Partial Reconfiguration Tutorial for the Intel® Agilex® F-Series FPGA Development Board

Updated for:
Intel® Quartus® Prime Design Suite 21.1
This application note demonstrates transformation of a simple, flat (non-partitioned) design into a hierarchical partial reconfiguration design and implementation of the design on the Intel® Agilex® F-Series FPGA development board.

The partial reconfiguration (PR) feature allows you to reconfigure a portion of the FPGA dynamically, while the remaining FPGA design continues to function. Hierarchical partial reconfiguration (HPR) is an extension of partial reconfiguration (PR) that allows you to contain a child PR partition within another parent PR partition. You can create multiple personas for both the child and parent partitions. You can nest the child partitions within their parent partitions. Reconfiguring a parent partition does not impact the operation in the static region, but replaces the child partitions of the parent region with default child partition personas. This methodology is effective in systems where multiple functions time-share the same FPGA device resources.

Partial reconfiguration provides the following advancements to a flat design:
  • Allows run-time design reconfiguration
  • Increases scalability of the design
  • Reduces system down-time
  • Supports dynamic time-multiplexing functions in the design
  • Lowers cost and power consumption through efficient use of board space

Implementation of this reference design requires basic familiarity with the Intel® Quartus® Prime FPGA implementation flow and knowledge of the primary Intel® Quartus® Prime project files. This tutorial uses the Intel® Agilex® F-Series FPGA development board on the bench, outside of the PCIe* slot in your workstation.