AN 954: Hierarchical Partial Reconfiguration Tutorial: for the Intel® Agilex® F-Series FPGA Development Board
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Reference Design Files
The files required for this tutorial are available in the following location:
https://github.com/intel/fpga-partial-reconfig
- Click Code > Download ZIP.
- Unzip the fpga-partial-reconfig-master.zip file.
- Navigate to the tutorials/agilex_pcie_devkit_blinking_led_hpr sub-folder to access the reference design.
File Name | Description |
---|---|
top.sv | Top-level file containing the flat implementation of the design. This module instantiates the blinking_led sub-partition and the top_counter module. |
top_counter.sv | Top-level 32-bit counter that controls LED[1] directly. The registered output of the counter controls LED[0], and powers LED[2] and LED[3] via the blinking_led module. |
blinking_led.sdc | Defines the timing constraints for the project. |
blinking_led.sv | In this tutorial, you convert this module into a parent PR partition. The module receives the registered output of top_counter module, which controls LED[2] and LED[3]. |
blinking_led.qpf | Intel® Quartus® Prime project file containing the list of all the revisions in the project. |
blinking_led.qsf | Intel® Quartus® Prime settings file containing the assignments and settings for the project. |
The hpr folder contains the complete set of files you create using this application note. Reference these files at any point during the walkthrough.