AN 954: Hierarchical Partial Reconfiguration Tutorial: for the Intel® Agilex® F-Series FPGA Development Board

ID 683687
Date 8/04/2021

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Reference Design Files

The files required for this tutorial are available in the following location:

To download the files:
  1. Click Code > Download ZIP.
  2. Unzip the file.
  3. Navigate to the tutorials/agilex_pcie_devkit_blinking_led_hpr sub-folder to access the reference design.
The flat folder consists of the following files:
Table 1.  Reference Design Files
File Name Description

Top-level file containing the flat implementation of the design. This module instantiates the blinking_led sub-partition and the top_counter module. Top-level 32-bit counter that controls LED[1] directly. The registered output of the counter controls LED[0], and powers LED[2] and LED[3] via the blinking_led module.

Defines the timing constraints for the project. In this tutorial, you convert this module into a parent PR partition. The module receives the registered output of top_counter module, which controls LED[2] and LED[3].

Intel® Quartus® Prime project file containing the list of all the revisions in the project.


Intel® Quartus® Prime settings file containing the assignments and settings for the project.


The hpr folder contains the complete set of files you create using this application note. Reference these files at any point during the walkthrough.

Figure 2. Reference Design Files