AN 954: Hierarchical Partial Reconfiguration Tutorial: for the Intel® Agilex® F-Series FPGA Development Board

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ID 683687
Date 8/04/2021
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Document Table of Contents
Document Table of Contents x
Hierarchical Partial Reconfiguration Tutorial for the Intel® Agilex® F-Series FPGA Development Board
Hierarchical Partial Reconfiguration Tutorial for the Intel® Agilex® F-Series FPGA Development Board x
Reference Design Overview Reference Design Requirements Reference Design Files Reference Design Walkthrough Document Revision History for AN 954: Hierarchical Partial Reconfiguration Tutorial for Intel® Agilex® F-Series FPGA Development Board
Reference Design Walkthrough x
Step 1: Getting Started Step 2: Creating a Child Level Submodule Step 3: Creating Design Partitions Step 4: Allocating Placement and Routing Region for PR Partitions Step 5: Defining Personas Step 6: Creating Revisions Step 7: Compiling the Base Revision Step 8: Preparing the PR Implementation Revisions for Parent PR Partition Step 9: Preparing the PR Implementation Revisions for Child PR Partitions Step 10: Programming the Board Modifying an Existing Persona Adding a New Persona to the Design
Step 6: Creating Revisions x
Setting the Base Revision Type Creating Implementation Revisions
Step 10: Programming the Board x
Programming the Child PR Region
Hierarchical Partial Reconfiguration Tutorial for the Intel® Agilex® F-Series FPGA Development Board
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Reference Design Requirements

This reference design requires the following:

  • Intel® Quartus® Prime Pro Edition software version 21.1 for the design implementation.
  • Intel® Agilex® F-Series FPGA development kit (DK-DEV-AGF014E3ES or DK-DEV-AGF014E2ES) for the FPGA implementation.
Level Two Title