AN 954: Hierarchical Partial Reconfiguration Tutorial: for the Intel® Agilex® F-Series FPGA Development Board
ID
683687
Date
8/04/2021
Public
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Step 1: Getting Started
Step 2: Creating a Child Level Submodule
Step 3: Creating Design Partitions
Step 4: Allocating Placement and Routing Region for PR Partitions
Step 5: Defining Personas
Step 6: Creating Revisions
Step 7: Compiling the Base Revision
Step 8: Preparing the PR Implementation Revisions for Parent PR Partition
Step 9: Preparing the PR Implementation Revisions for Child PR Partitions
Step 10: Programming the Board
Modifying an Existing Persona
Adding a New Persona to the Design
Reference Design Overview
This reference design used in this tutorial consists of one 32-bit counter. At the board level, the design connects the clock to a 50MHz source, and connects the output to four LEDs connected to the FPGA. Selecting the output from particular counter bits causes the LEDs to blink at a specific frequency.
Figure 1. Flat Reference Design without PR Partitioning