Intel Agilex® 7 Configuration User Guide

ID 683673
Date 2/05/2024
Public
Document Table of Contents

3.1.7.2. Designing with the Parallel Flash Loader II Intel® FPGA IP for Avalon-ST Single Device Configuration

This section describes the procedures on how to use the Parallel Flash Loader II Intel® FPGA IP.

To target a MAX® II, MAX® V, or Intel® MAX® 10 device requires the use of Intel® Quartus® Prime Standard Edition software whereas targeting a Intel Agilex® 7 requires Intel® Quartus® Prime Pro Edition software.

The process of creating the Avalon-ST single device configuration design targeting a MAX® II, MAX® V, or Intel® MAX® 10 device involves three steps.
  1. Generate the AVST design for the MAX® device with the default option address.
  2. Create the Intel Agilex® 7 .pof file in setting the appropriate option bits.
  3. Regenerate the Parallel Flash Loader II Intel® FPGA IP with the option bits used to generate the Intel Agilex® 7 .pof file and recompile the Intel® MAX® 10 design.

You can find an Intel® MAX® 10 system design example that implements theParallel Flash Loader II Intel® FPGA IP for AVST x32 configuration mode in the installer package of the Intel Agilex® 7 F-Series Transceiver-SoC Development Kit.

Figure 31. Process for Using the Parallel Flash Loader II Intel® FPGA IP Figure shows the process for using the Parallel Flash Loader II Intel® FPGA IP, using MAX® II as an example.