Intel Agilex® 7 Configuration User Guide

ID 683673
Date 2/05/2024
Public
Document Table of Contents
Give Feedback

4. Including the Reset Release Intel® FPGA IP in Your Design

Intel requires that you either use the Reset Release Intel® FPGA IP to hold your design in reset until configuration is complete.

The Reset Release Intel® FPGA IP is available in the Intel® Quartus® Prime software. This IP consists of a single output signal, nINIT_DONE. The nINIT_DONE signal is the core version of the INIT_DONE pin and has the same function in both FPGA First and HPS First configuration modes. Intel recommends that you hold your design in reset while the nINIT_DONE signal is high or while the INIT_DONE pin is low. When you instantiate the Reset Release Intel® FPGA IP in your design, the SDM drives the nINIT_DONE signal. Consequently, the IP does not consume any FPGA fabric resources, but does require routing resources.

Figure 62.  Reset Release Intel® FPGA IP nINIT_DONE Internal Connection

View the video guide below for a quick walk-through to understand the importance of using Reset Release Intel® FPGA IP and how to include it in your design.