Intel Agilex® 7 Configuration User Guide

ID 683673
Date 2/05/2024
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2.7. Intel Agilex® 7 Configuration Time Estimation

This section describes configuration time for various configuration modes for different bitstream sizes. For example, in PCIe* designs, your system software may require the Intel Agilex® 7 device to enter user mode in less than 1 second to return a successful completion status for a valid configuration request. Use the values referenced below to determine the configuration mode that best suits your design requirements.

The table provides time estimates for the full FPGA configuration only. In HPS enabled designs, the table also considers the FPGA configuration first mode. Note that the HPS boot first mode in HPS enabled designs is not considered. Also, the CvP periphery image configuration is not considered.

The following conditions were used to estimate the configuration time values:
  • Set the VID mode of operation to PMBus Master mode
  • Use Intersil ISL68137 regulator to regulate the PMBus
  • Set configuration clock source to OSC_CLK_1 with 25/100/125 MHz
  • No advanced security features were enabled
  • For AVST x8/x16/x32 configuration modes, set the AVST_CLK to 125 MHz. The external host controller supplies the AVST_DATA by asserting the AVST_VALID signal high whenever the AVST_READY signal is high.
  • For AS x4 configuration mode, set the AS_CLK to 166 MHz. Use a Micron device with a 2 Gb density range QSPI flash memory.
Table 15.  Configuration Time for Various Configuration Modes The configuration file size is dependent on the user design complexity. In general, higher logic utilization with randomized logic patterns produces larger configuration file sizes. Regardless of the configuration file size, the decompression block must decompress the bitstream and configure the same number of CRAM bits within the device. A higher bandwidth configuration scheme like in the AVST x32 may send larger configuration files in shorter time. However, there is little to no benefit with sending a small configuration file when using higher bandwidth configuration schemes as the bottleneck is the time taken for decompression and not the time taken to send over the bitstream to the device. The data in this table is preliminary.
Device RBF File Size (MB) Configuration Time Estimation (ms)
AS x4 7 AVST x8 AVST x16 AVST x32

AGF 006

AGF 008

2.6 180 170 170 170
10.7 300 250 200 180
19.5 430 330 250 200

AGF 012

AGF 014

2.5 250 170 150 150
26 540 330 220 190
33 620 380 240 210

AGF 022

AGF 027

AGI 022

AGI 027

3.6 430 380 370 370
28 720 540 440 410
61 1,110 760 520 460

AGF 019

AGF 023

AGI 019

AGI 023

5.7 440 410 360 360
27 700 570 430 410
50 990 740 510 460

AGM 032

AGM 039

3.3 460 400 400 400
42 950 680 520 480
81 1440 970 650 560

AGI 035

AGI 040

5.3 570 570 570 560
41.9 1100 880 690 600
91.4 1840 1350 940 730

AGI 041

4.2 400 400 400 400
34.1 830 650 500 430
74.5 1430 1040 700 530
7 For non-Micron QSPI flash memory, the AS x4 configuration time increases by 126 ms.