Intel Agilex® 7 Configuration User Guide

ID 683673
Date 2/05/2024
Public
Document Table of Contents

3.1.7.3.1. Controlling Avalon-ST Configuration with Parallel Flash Loader II Intel® FPGA IP

The Parallel Flash Loader II Intel® FPGA IP in the host determines when to start the configuration process, read the data from the flash memory device, and configure the Intel Agilex® 7 device using the Avalon-ST configuration scheme.
Figure 32. FPGA Configuration with Flash Memory Data

You can use the Parallel Flash Loader II Intel® FPGA IP to either program the flash memory devices, configure your FPGA, or both. To perform both functions, create separate Parallel Flash Loader II Intel® FPGA IP functions if any of the following conditions apply to your design:

  • You modify the flash data infrequently.
  • You have JTAG or In-System Programming (ISP) access to the configuration host.
  • You want to program the flash memory device with non-Intel FPGA data, for example initialization storage for an ASSP. You can use the Parallel Flash Loader II Intel® FPGA IP to program the flash memory device for the following purposes:
    • To write the initialization data
    • To store your design source code to implement the read and initialization control with the host logic