Intel Agilex® 7 Configuration User Guide

ID 683673
Date 2/05/2024
Public
Document Table of Contents

3.1.7.1.5. Implementing Page Mode and Option Bits in the CFI Flash Memory Device

The following figure shows a sample layout of a .pof with three pages. The end addresses depend on the density of the flash memory device. For different density devices refer to the Byte Address Range for CFI Flash Memory Devices with Different Densities table below. The option bits follow the configuration data in memory.

Figure 29. Implementing Page Mode and Option Bits in the CFI Flash Memory Device

The following figure shows the layout of the option bits for a single page. Because the start address must be on an 8 KB boundary, bits 0-12 of the page start address are set to zero and are not stored in the option bits.

Figure 30. Page Start Address, End Address, and Page-Valid Bit Stored as Option BitsThe Page-Valid bits indicate whether each page is successfully programmed. The Parallel Flash Loader II Intel® FPGA IP sets the Page-Valid bits after successfully programming the pages.
Table 24.  Byte Address Range for CFI Flash Memory Devices with Different Densities
CFI Device (Megabit) Address Range
8 0x00000000x00FFFFF
16 0x00000000x01FFFFF
32 0x00000000x03FFFFF
64 0x00000000x07FFFFF
128 0x00000000x0FFFFFF
256 0x00000000x1FFFFFF
512 0x00000000x3FFFFFF
1024 0x00000000x7FFFFFF