ASMI Parallel II Intel® FPGA IP User Guide

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ID 683669
Date 10/09/2023
Public
Document Table of Contents
Document Table of Contents x
ASMI Parallel II Intel® FPGA IP User Guide
ASMI Parallel II Intel® FPGA IP User Guide x
Release Information Ports Parameters Register Map Operations ASMI Parallel II Intel® FPGA IP Use Case Examples ASMI Parallel II Intel® FPGA IP User Guide Archives Document Revision History for the ASMI Parallel II Intel® FPGA IP User Guide
Operations x
Control Status Register Operations Memory Operations
ASMI Parallel II Intel® FPGA IP Use Case Examples x
Example 1: Read the Silicon ID of the Configuration Devices Example 2: Read and Write One Word of Data at Address H'40000000 Example 3: Erase Sector 64 Example 4: Perform Sector Protect at Sectors (0 to 127) Example 5: Read and Clear Flag Status Register Example 6: Read and Write nvcr
ASMI Parallel II Intel® FPGA IP User Guide

Ports

Figure 1. Ports Block Diagram
Table 2.  Ports Description
Signal Width Direction Description
Avalon® Memory-Mapped Slave Interface for CSR (avl_csr)
avl_csr_address 6 Input Avalon® memory-mapped interface address bus. The address bus is in word addressing.
avl_csr_read 1 Input Avalon® memory-mapped interface read control to the CSR.
avl_csr_readdata 32 Output Avalon® memory-mapped interface read data bus from the CSR.
avl_csr_write 1 Input Avalon® memory-mapped interface write control to the CSR.
avl_csr_writedata 32 Input Avalon® memory-mapped interface write data bus to CSR.
avl_csr_waitrequest 1 Output Avalon® memory-mapped interface waitrequest control from the CSR.
avl_csr_readdatavalid 1 Output Avalon® memory-mapped interface read data valid that indicates the CSR read data is available.
Avalon® Memory-Mapped Slave Interface for Memory Access (avl_ mem)
avl_mem_write 1 Input Avalon® memory-mapped interface write control to the memory
avl_mem_burstcount 7 Input Avalon® memory-mapped interface burst count for the memory. The value range from 1 to 64 (maximum page size).
avl_mem_waitrequest 1 Output Avalon® memory-mapped interface waitrequest control from the memory.
avl_mem_read 1 Input Avalon® memory-mapped interface read control to the memory
avl_mem_address N Input

Avalon® memory-mapped interface address bus. The address bus is in word addressing.

The width of the address depends on the flash memory density used.
avl_mem_writedata 32 Input Avalon® memory-mapped interface write data bus to the memory
avl_mem_readddata 32 Output Avalon® memory-mapped interface read data bus from the memory.
avl_mem_rddata_valid 1 Output Avalon® memory-mapped interface read data valid that indicates the memory read data is available.
avl_mem_byteenable 4 Input Avalon® memory-mapped interface write data enable bus to memory. During bursting mode, byteenable bus is logic high, 4’b1111.
Clock and Reset
clk 1 Input Input clock to clock the IP. 1
reset_n 1 Input Asynchronous reset to reset the IP.2
Conduit Interface
qspi_pins_data 3 4 Bidirectional Input or output port to feed data from the flash device.
qspi_pins_dclk 3 1 Output Provides clock signal to the flash device.
qspi_pins_ncs 3 1 Output

Provides the ncs signal to the flash device.

Supports Stratix® V, Arria® V, Cyclone® V, and older devices.

3 Output

Provides the ncs signal to the flash device.

Supports Intel® Arria® 10 and Intel® Cyclone® 10 GX devices.

atom_ports_dclk 4 1 Output

Provides the clock signal to the flash device through the ASMI block.

Connects to dclk of the ASMI block.

atom_ports_ncs 4 1/3 Output

Provides the ncs signal to the flash device through the ASMI block.

Connects to sce of the ASMI block.

atom_ports_oe 4 1 Output

Active-low signal to enable the dclk and ncs pins to the flash through the ASMI block.

Connects to oe of the ASMI block.

atom_ports_dataout 4 4 Output

Control signals from your FPGA design to the AS data pin for sending data into the flash through the ASMI block.

For the following devices, connect atom_ports_dataout[0:3] to data0out, data1out, data2out, and data3out of the ASMI block.
  • Intel® Arria® 10
  • Intel® Cyclone® 10 GX
  • Arria® V
  • Arria® V GZ
  • Cyclone® V
  • Stratix® V
For the following devices, connect the atom_ports_dataout[0] to sdoin of the ASMI block.
  • Intel® Cyclone® 10 LP
  • Cyclone® IV GX
  • Cyclone® IV E
  • Stratix® IV
  • Arria® II
  • Arria® II GZ
atom_ports_dataoe 4 4 Output

Controls dedicated Active Serial data pins to either input or output.

  • b’0 – AS data pin as input
  • b’1 – AS data pin as output

For all devices, connect atom_ports_dataoe[0:3] to data0oe, data1oe, data2oe, and data3oe of the ASMI block

atom_ports_datain 4 4 Input

Receives data from the AS data pin through the ASMI block to the FPGA design.

For the following devices, connect atom_ports_datain[0:3] to data0in, data1in, data2in, and data3in of the ASMI block.
  • Intel® Arria® 10
  • Intel® Cyclone® 10 GX
  • Arria® V
  • Arria® V GZ
  • Cyclone® V
  • Stratix® V
For the following devices, connect atom_ports_datain[1] to data0out of the ASMI block.
  • Intel® Cyclone® 10 LP
  • Cyclone® IV GX
  • Cyclone® IV E
  • Stratix® IV
  • Arria® II
  • Arria® II GZ
Related Information
1 You can set the clock frequency to lower or equal to 50 MHz.
2 Hold the signal for at least one clock cycle to reset the IP.
3 Available when you enable the Enable SPI pins interface parameter.
4 Available when you enable the Disable dedicated Active Serial interface parameter.
Level Two Title