ASMI Parallel II Intel® FPGA IP User Guide

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ID 683669
Date 10/09/2023
Public
Document Table of Contents
Document Table of Contents x
ASMI Parallel II Intel® FPGA IP User Guide
ASMI Parallel II Intel® FPGA IP User Guide x
Release Information Ports Parameters Register Map Operations ASMI Parallel II Intel® FPGA IP Use Case Examples ASMI Parallel II Intel® FPGA IP User Guide Archives Document Revision History for the ASMI Parallel II Intel® FPGA IP User Guide
Operations x
Control Status Register Operations Memory Operations
ASMI Parallel II Intel® FPGA IP Use Case Examples x
Example 1: Read the Silicon ID of the Configuration Devices Example 2: Read and Write One Word of Data at Address H'40000000 Example 3: Erase Sector 64 Example 4: Perform Sector Protect at Sectors (0 to 127) Example 5: Read and Clear Flag Status Register Example 6: Read and Write nvcr
ASMI Parallel II Intel® FPGA IP User Guide

Register Map

Table 4.  Register Map
  • Each address offset in the following table represents 1 word of memory address space.
  • All registers have a default value of 0x0.
Offset Register Name R/W Field Name Bit Width Description
0 WR_ENABLE W WR_ENABLE 0 1 Write 1 to perform write enable.
1 WR_DISABLE W WR_DISABLE 0 1 Write 1 to perform write disable.
2 WR_STATUS W WR_STATUS 7:0 8 Contains the information to write to the status register.
3 RD_STATUS R RD_STATUS 7:0 8 Contains the information from read status register operation.
4 SECTOR_ERASE W Sector Value 23:0 or 31:0 24 or 32 Contain the sector address to be erased depending on device density.6
5 SUBSECTOR_ERASE W Subsector Value 23:0 or 31:0 24 or 32 Contains the subsector address to be erased depending on device density.7
6 - 7 Reserved
8 CONTROL W/R CHIP SELECT 7:4 4 Selects flash device. The default value is 0, which targets first flash device. To select second device, set the value to 1, to select the third device, set the value to 2.
Reserved
W/R DISABLE 0 1 Set this to 1 to disable the SPI signals of the IP by putting all output signal to high-Z state. This can be used to share bus with other devices.
9 - 12 Reserved

13

 WR_NON_VOLATILE_CONF_REG W NVCR value 15:0 16 Writes value to non-volatile configuration register.
14 RD_NON_VOLATILE_CONF_REG R NVCR value 15:0 16 Reads value from non-volatile configuration register
15 RD_ FLAG_ STATUS_REG R RD_ FLAG_ STATUS_REG 8 8 Reads flag status register
16 CLR_FLAG_ STATUS REG W CLR_FLAG_ STATUS REG 8 8 Clears flag status register

17

 BULK_ERASE W BULK_ERASE 0 1 Write 1 to erase entire chip (for single-die device). 8

18

 DIE_ERASE W DIE_ERASE 0 1

Write 1 to erase entire die (for stack-die device).8

19 4BYTES_ADDR_EN W 4BYTES_ADDR_EN 0 1 Write 1 to enter 4 bytes address mode
20 4BYTES_ADDR_EX W 4BYTES_ADDR_EX 0 1 Write 1 to exit 4 bytes address mode
21 SECTOR_PROTECT W Sector protect value 7:0 8 Value to write to status register to protect a sector. 9
22 RD_MEMORY_CAPACITY_ID R Memory capacity value 7:0 8 Contains the information of memory capacity ID.
23 - 32 Reserved
Related Information
6 You only need to specify any address within the sector and the IP will erase that particular sector.
7 You only need to specify any address within the subsector and the IP will erase that particular subsector.
8 You only need to specify any address within the die and the IP will erase that particular die.
9 For EPCQ and EPCQ-L devices, the block protect bit are bit [2:4] and [6] and the top/bottom (TB) bit is bit 5 of the status register. For EPCQ-A devices. the block protect bit are bit [2:4] and the TB bit is bit 5 of the status register.
Level Two Title