ASMI Parallel II Intel® FPGA IP User Guide

ID 683669
Date 10/09/2023

Control Status Register Operations

You can perform a read or write to a specific address offset using the Control Status Register (CSR).

To execute the read or write operation for the control status register, follow these steps:

  1. Assert the avl_csr_write or avl_csr_read signal while the avl_csr_waitrequest signal is low (if the waitrequest signal is high, the avl_csr_write or avl_csr_read signal must to be kept high until the waitrequest signal goes low).
  2. At the same time, set the address value on the avl_csr_address bus. If it is a write operation, set the value data on the avl_csr_writedata bus together with the address.
  3. If it is a read transaction, wait until the avl_csr_readdatavalid signal is asserted high to retrieve the read data.
  • For operations that require write value to flash, you must perform the write enable operation first.
  • You must read the flag status register every time you issue a write or erase command.
  • If multiple flash devices are used, you must write to the chip select register to select the correct chip select before performing any operation to the specific flash device.
Figure 2. Read Memory Capacity Register Waveform Example
Figure 3. Write Enable Register Waveform Example