ASMI Parallel II Intel® FPGA IP User Guide

Download PDF
ID 683669
Date 10/09/2023
Public
Document Table of Contents
Document Table of Contents x
ASMI Parallel II Intel® FPGA IP User Guide
ASMI Parallel II Intel® FPGA IP User Guide x
Release Information Ports Parameters Register Map Operations ASMI Parallel II Intel® FPGA IP Use Case Examples ASMI Parallel II Intel® FPGA IP User Guide Archives Document Revision History for the ASMI Parallel II Intel® FPGA IP User Guide
Operations x
Control Status Register Operations Memory Operations
ASMI Parallel II Intel® FPGA IP Use Case Examples x
Example 1: Read the Silicon ID of the Configuration Devices Example 2: Read and Write One Word of Data at Address H'40000000 Example 3: Erase Sector 64 Example 4: Perform Sector Protect at Sectors (0 to 127) Example 5: Read and Clear Flag Status Register Example 6: Read and Write nvcr
ASMI Parallel II Intel® FPGA IP User Guide

Parameters

Table 3.  Parameter Settings
Parameter Legal Values Descriptions
Configuration device type

EPCQ16,

EPCQ32,

EPCQ64,

EPCQ128,

EPCQ256,

EPCQ512,

EPCQ-L256,

EPCQ-L512,

EPCQ-L1024,

EPCQ4A,

EPCQ16A,

EPCQ32A,

EPCQ64A,

EPCQ128A

 Specifies the EPCQ, EPCQ-L, or EPCQ-A device type you want to use.
Choose I/O mode

NORMAL

STANDARD

DUAL

QUAD

Selects extended data width when you enable the Fast Read operation.
Disable dedicated Active Serial interface — Routes the ASMIBLOCK signals to the top level of your design.
Enable SPI pins interface — Translates the ASMIBLOCK signals to the SPI pin interface.
Enable flash simulation model — Uses the default EPCQ 1024 simulation model for simulation. If you are using a third-party flash device, refer to AN 720: Simulating the ASMI Block in Your Design to create a wrapper to connect the flash model with the ASMI Block.
Number of Chip Select used

1

2 5

35

Selects the number of chip select connected to the flash.
Related Information
5 Only supported in Intel® Arria® 10 devices, Intel® Cyclone® 10 GX devices, and other devices with Enable SPI pins interface enabled.
Level Two Title