ASMI Parallel II Intel® FPGA IP User Guide

ID 683669
Date 10/09/2023

Memory Operations

The ASMI Parallel II Intel® FPGA IP memory interface supports bursting and direct flash memory access. During the direct flash memory access, the IP performs the following steps to allow you to perform any direct read or write operation:

  • Write enable for the write operation
  • Check flag status register to make sure the operation has been completed at the flash
  • Release the waitrequest signal when the operation is completed

Memory operations are similar to the Avalon® memory-mapped interface operations. You must set the correct value at the address bus, write data if it is a write transaction, drive the burst count value to 1 for single transaction or your desired burst count value, and trigger the write or read signal.

Figure 4. 8-Word Write Burst Waveform Example
Figure 5. 8-Word Reading Burst Waveform Example
Figure 6. 1-Byte Write byteenable = 4’b0001 Waveform Example