ASMI Parallel II Intel® FPGA IP User Guide

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ID 683669
Date 10/09/2023
Public
Document Table of Contents
Document Table of Contents x
ASMI Parallel II Intel® FPGA IP User Guide
ASMI Parallel II Intel® FPGA IP User Guide x
Release Information Ports Parameters Register Map Operations ASMI Parallel II Intel® FPGA IP Use Case Examples ASMI Parallel II Intel® FPGA IP User Guide Archives Document Revision History for the ASMI Parallel II Intel® FPGA IP User Guide
Operations x
Control Status Register Operations Memory Operations
ASMI Parallel II Intel® FPGA IP Use Case Examples x
Example 1: Read the Silicon ID of the Configuration Devices Example 2: Read and Write One Word of Data at Address H'40000000 Example 3: Erase Sector 64 Example 4: Perform Sector Protect at Sectors (0 to 127) Example 5: Read and Clear Flag Status Register Example 6: Read and Write nvcr
ASMI Parallel II Intel® FPGA IP User Guide

Document Revision History for the ASMI Parallel II Intel® FPGA IP User Guide

Document Version Intel® Quartus® Prime Version IP Version Changes
2023.10.09 18.0 18.0
  • Updated the Ports section:
    • Signal name avl_csr_addr to avl_csr_address.
    • Signal name avl_csr_rddata to avl_csr_readdata.
    • Signal name avl_csr_rddata_valid to avl_csr_readdatavalid.
    • Signal name avl_mem_addr to avl_mem_address.
    • Signal name avl_mem_byteenble to avl_mem_byteenable.
    • Signal name qspi_dataout to qspi_pins_data.
    • Signal name qspi_dclk to qspi_pins_dclk.
    • Signal name qspi_scein to qspi_pins_ncs.
    • Added atom ports and footnotes to the Ports Description table.
  • Updated the ASMI Parallel II Intel® FPGA IP User Guide Archives topic.
2020.07.29 18.0 18.0
  • Updated the document title to ASMI Parallel II Intel® FPGA IP User Guide.
  • Updated Table 2: Parameter Settings in section Parameters.
2018.09.24 18.0 18.0
  • Added information on the applications and support for the ASMI Parallel II Intel® FPGA IP core.
  • Added a note to refer to the Generic Serial Flash Interface Intel FPGA IP Core User Guide.
  • Added the ASMI Parallel II Intel® FPGA IP Core Use Case Examples section.
2018.05.07 18.0 18.0
  • Renamed Altera ASMI Parallel II IP core to ASMI Parallel II Intel® FPGA IP core per Intel rebranding.
  • Added support for EPCQ-A devices.
  • Added a note to the clk signal in the Ports Description table.
  • Updated the description for the qspi_scein signal in the Ports Description table.
  • Added a note to the SECTOR_PROTECT register in the Register Map table.
  • Updated the bit and width for SECTOR_ERASE and SUBSECTOR_ERASE registers in the Register Map table.
  • Updated the bit and width for SECTOR_PROTECT register in the Register Map table.
  • Updated the description for the CHIP SELECT option of the CONTROL register in the Register Map table.
  • Updated the footnotes for the SECTOR_ERASE, SUBSECTOR_ERASE, BULK_ERASE, and DIE_ERASE registers in the Register Map table.
  • Updated the description for the vl_mem_addr signal in the Ports Description table.
  • Minor editorial edits.
Date Version Changes
May 2017 2017.05.08 Initial release.
Level Two Title