AN 845: Signal Tap Tutorial for Intel® Arria® 10 Partial Reconfiguration Design

ID 683662
Date 1/28/2022

2. Tutorial Walkthrough

This tutorial describes preparing the blinking_led design for debug with the Signal Tap Logic Analyzer.
This Application Note does not describe turning a non-PR design to a PR design. Refer to AN 797: Partially Reconfiguring a Design on Intel® Arria® 10 GX FPGA Development Board for examples of the following tasks:
  • Creating a design partition
  • Allocating placement and routing regions for a PR partition
  • Defining personas
  • Creating project revisions
  • Preparing PR implementation revisions

Process Description

To tap signals in a PR design, you extend the debug fabric to the PR regions when creating the base revision, and then define debug components for the implementation revisions.

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