2.1. Step 1: Getting Started 2.2. Step 2: Preparing the Base Revision 2.3. Step 3: Preparing the Implementation Revisions for Debugging 2.4. Step 4: Configuring Signal Tap Logic Analyzer 2.5. Step 5: Generating Programming Files 2.6. Step 6: Programming the FPGA Device 2.7. Step 7: Performing Data Acquisition
2.2. Step 2: Preparing the Base Revision
To prepare the base revision, extend the debug fabric to the PR regions that you want to debug.
To extend the debug fabric to the PR regions that you want to debug:
- Instantiate the SLD JTAG Bridge Agent in the static region
- Instantiate the SLD JTAG Bridge Host in the default persona of the PR region
For the debug logic to be function properly after partial reconfiguration, the design needs a reset signal. To add a reset signal to the design, instantiate the Intel Configuration Reset Release Endpoint to Debug Logic IP in the PR region.
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