AN 845: Signal Tap Tutorial for Intel® Arria® 10 Partial Reconfiguration Design
                    
                        ID
                        683662
                    
                
                
                    Date
                    1/28/2022
                
                
                    Public
                
            
                        
                        
                            
                            
                                2.1. Step 1: Getting Started
                            
                        
                            
                                2.2. Step 2: Preparing the Base Revision
                            
                            
                        
                            
                            
                                2.3. Step 3: Preparing the Implementation Revisions for Debugging
                            
                        
                            
                                2.4. Step 4: Configuring Signal Tap Logic Analyzer
                            
                            
                        
                            
                            
                                2.5. Step 5: Generating Programming Files
                            
                        
                            
                            
                                2.6. Step 6: Programming the FPGA Device
                            
                        
                            
                            
                                2.7. Step 7: Performing Data Acquisition
                            
                        
                    
                1.3. Tutorial Design Description
   The design for this tutorial consists of one 32-bit counter. At the board level, the design connects the clock to a 50MHz source, and connects the output to four LEDs on the FPGA. Selecting the output from the counter bits in a specific sequence causes the LEDs to blink at a specific frequency. 
   
 
 
    Figure 2. Flat Reference Design without PR Partitioning