Intel® Quartus® Prime Pro Edition User Guide: Design Optimization

ID 683641
Date 8/01/2023

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If the design requires a global signal, consider adding half a cycle to timing by using a negative-edge triggered register to generate the signal, and use a multicycle setup constraint.
Figure 57. Negative-Edge Triggered Register
Figure 58. Multicycle Setup Constraint
set_multicycle_path -from <generating_register> -setup -end 2