Intel® Quartus® Prime Pro Edition User Guide: Design Optimization

ID 683641
Date 8/01/2023

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6.5.1. Correct Design Assistant Rule Violations

After running any stage of the Compiler, review the Design Assistant reports to analyze any design rule violations and view recommendations to correct failing paths.
When enabled, the Intel® Quartus® Prime Design Assistant automatically runs during compilation and reports any violations against a set of Intel FPGA-recommended design guidelines. Design Assistant rules include Timing Closure, Clocking, CDC, reset, and floorplanning.

You can customize the Design Assistant for your design characteristics and reporting requirements. Run Design Assistant in Compilation Flow mode to view the violations relevant for Compiler stages. Run in analysis mode from tools like the Timing Analyzer and Chip Planner to cross-probe from an individual rule violation to more information.

Follow these steps to enable and run Design Assistant and view results following compilation:
  1. Click Assignments > Settings > Design Assistant Rules Settings.
    Figure 34. Design Assistant Rules Settings
  2. To enable Design Assistant checking during compilation, turn on Enable Design Assistant execution during compilation.
  3. To run Design Assistant during compilation, run one or more modules of the Compiler. Design Assistant reports results for each stage in the Compilation Report.
  4. To view the results for each rule, click the rule in the Rules list. A description of the rule and design recommendations for correction appear.
  5. For timing path-related rule violations, right-click the node or path, and then click Report Timing (Extra Info) or Report Path (Extra Info). The Timing Analyzer loads and automatically displays the Report Timing or Report Path data related to the rule violation, allowing you to probe every aspect of the violation. Report Path can report timing even for paths that are cut.
    Figure 35. Cross Probing From Design Assistant Rule Violations to Timing Analyzer