Intel® Quartus® Prime Pro Edition User Guide: Design Optimization

ID 683641
Date 8/01/2023

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6.5.2. Implement Fast Forward Timing Closure Recommendations

In traditional FPGA timing closure flows, the starting point for most design analysis is the critical path. Due to the nature of Intel® Hyperflex™ architecture and the availability of the Hyper Retimer, it is best to start you timing closure activities from the Retiming Limit Report. Provide the Hyper-Retimer as many optimization opportunities as possible, before having to look into more time intensive and potentially manual timing closure techniques.