Nios® V Processor Reference Manual

ID 683632
Date 12/11/2023

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Document Table of Contents

2.3.3. Reset and Debug Signals

Interface Type Description
reset Reset A global hardware reset input signal that forces the Nios® V processor to reset immediately.
cpu_resetreq Conduit An optional local reset ports which appear after you enable Add Reset Request Interface parameter. The signal consists of an input resetreq signal and an output ack signal that trigger the Nios® V processor to reset without affecting other components in a Nios® V processor system.
  • You can request a reset to the Nios® V processor core by asserting the resetreq signal.
  • The resetreq signal must remain asserted until the processor asserts ack signal. Failure for the signal to remain asserted can cause the processor to be in a non-deterministic state.
  • Assertion of the resetreq signal in debug mode has no effect on the processor's state.
  • The Nios® V processor responds that the reset is successful by asserting the ack signal.
  • After the processor is successfully reset, the assertion of the ack signal can happen multiple times periodically until the de-assertion of the resetreq signal.
Figure 3.  Nios® V/c Processor Reset Network