Nios® V Processor Reference Manual

ID 683632
Date 12/11/2023

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Document Table of Contents Data Manager Port

The Nios® V/m processor data bus is implemented as a 32-bit AMBA* 4 AXI-Lite manager port. The data manager port performs two functions:

  • Read data from memory or a peripheral when the processor executes a load instruction.
  • Write data to memory or a peripheral when the processor executes a store instruction.

axsize signal value indicates the load/store instruction size- byte (LB/SB), halfword (LH/SH) or word (LW/SW). Address on axaddr signal is always aligned to size of the transfer. For store instructions, respective writes strobe bits are asserted to indicate bytes being written.

Nios® V/m processor core does not support speculative issue of load/store instruction. Hence, a core can issue only one load or store instruction and waits until the issued instruction is complete.

Table 33.  Data Interface Signals
Interface Signal Role Width Direction
Write Address Channel awaddr Store address [31:0] Output
awprot Unused [2:0] Output
awvalid Store address valid 1 Output
awready Store address ready (from memory) 1 Input
Write Data Channel wvalid Store data valid 1 Output
wdata Store data [31:0] Output
wstrb Byte position in word [3:0] Output
wready Store data ready (from memory) 1 Input
Write Response Channel bvalid Store response valid 1 Input
bresp Store response: Non-zero value denotes store access fault exception. [1:0] Input
bready Constant 1 1 Output
Read Address Channel araddr Load address [31:0] Output
arprot Unused [2:0] Output
arvalid Load address valid 1 Output
arready Load address ready (from subordinates) 1 Input
Read Data Channel rdata Load data [31:0] Input
rvalid Load data valid 1 Input
rresp Load response: Non-zero value denotes instruction access fault exception [1:0] Input
rready Constant 1 1 Output