Nios® V Processor Reference Manual

ID 683632
Date 12/11/2023

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents Address Map

The address map for memories and peripherals in a Nios® V/m processor system is design dependent. The following addresses are part of the processor:
  1. Reset Address
  2. Debug Exception Address
  3. Exception Address
  4. Timer and Software Interrupt Address

You can specify the Reset Address and Debug Exception Address in Platform Designer during system configuration. You can modify the Exception Address stored in the mvtec register. mvtime and mtimecmp register controls the timer interrupt. The msip register bit controls the software interrupt.