Nios® V Processor Reference Manual

ID 683632
Date 12/11/2023

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Document Table of Contents Instruction and Data Tightly Coupled Memory

Nios® V/g processor supports the following TCMs:

  • Two instruction TCMs
  • Two data TCMs
Table 86.  TCM Characteristics
Characteristics TCM
4 bytes (1 words) per address line
  • Instruction TCM
  • Data TCM
Fixed memory latency of 1 cycle
  • Instruction TCM
  • Data TCM
Configurable size of 0 (Disabled) to 512MBytes
  • Instruction TCM
  • Data TCM
Configurable 32-bits base address
  • Instruction TCM
  • Data TCM
Supports memory initialization using MIF or HEX file
  • Instruction TCM
  • Data TCM
Read-only permission for processor core Instruction TCM
Read/Write permission for external AXI4-Lite manager Instruction TCM
Read/Write permission for processor core and external AXI4-Lite manager Data TCM
Table 87.  Tightly Coupled Memory Interface Signals
Interface Signal Role Width Direction
Write Address Channel awaddr Write address Width = log (tcm_size)/log 2 9 Input
awprot Unused [2:0] Input
awvalid Write address valid 1 Input
awready Write address ready (from TCM) 1 Output
Write Data Channel wvalid Write data valid 1 Input
wdata Write data [31:0] Input
wstrb Byte position in word [3:0] Input
wready Write data ready (from TCM) 1 Output
Write Response Channel bvalid Write response valid 1 Output
bresp Write response: Non-zero value denotes store access fault exception [1:0] Output
bready Write response ready (from external manager) 1 Input
Read Address Channel araddr Read address Width = log (tcm_size)/log 29 Input
arprot Unused [2:0] Input
arvalid Read address valid 1 Input
arready Read address ready (from TCM) 1 Output
Read Data Channel rdata Read data [31:0] Output
rvalid Read data valid 1 Output
rresp Read data response: Non-zero value denotes load access fault exception [1:0] Output
rready Read data ready (from TCM) 1 Input
9 The width of the Write and Read Addresses depends on the selected TCM size.