Nios® V Processor Reference Manual

ID 683632
Date 12/11/2023
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Document Table of Contents
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4.1. Processor Performance Benchmarks

Table 67.   Nios® V/g Processor Performance Benchmarks in Intel FPGA Devices for Intel® Quartus® Prime Pro Edition Software
FPGA Used fMAX (MHz) Logic Size (ALM) Architecture Performance
DMIPS/MHz Ratio CoreMark/MHz Ratio
Intel® Cyclone® 10 236 1834 0.942 1.487
Intel® Arria® 10 240 1837
Intel® Stratix® 10 275 2045
Intel Agilex® 7 334 1989
Table 68.  Benchmark Parameters for Intel® Quartus® Prime Pro Edition Software
Parameter Settings/Description
Intel® Quartus® Prime seed Maximum performance result are based on 10 seed sweep from Intel® Quartus® Prime Pro Edition software version 23.4.
Device speed grade Fastest speed grade from each Intel FPGA device family.
Defined peripherals
  • Nios® V/g processor core (without debug module, internal timer, floating point unit, 4 KB instruction cache, and 4 KB data cache).
  • 128 KB on-chip memory for the instruction and data bus.
  • JTAG UART Intel® FPGA IP.
  • Interval Timer Core.
Toolchain Version
  • riscv32-unknown-elf-gcc (GCC) version 12.1.0
  • CMake Version: 3.27.1
Compiler configuration
  • Compiler flags: -03
  • Assembler options: -Wa -gdwarf2
  • Compile options: -Wall -Wformat-security -march=rv32im_zicbom -mabi=ilp32
Intel uses the same Intel® Quartus® Prime design example for maximum performance benchmark(fMAX) and logic size benchmarks. However, the compiler settings are different for each benchmarks:
  • fMAX benchmark: superior_performance_optimized_placement_effort
  • Logic size benchmark: area_aggressive
Note: Results may vary depending on the version of the Intel® Quartus® Prime software, the version of the Nios® V processor, compiler version, target device and the configuration of the processor. Additionally, any changes to the system logic design might change the performance and LE usage. All results are generated from design built with Platform Designer.
Table 69.   Nios® V/g Processor Performance Benchmarks in Intel FPGA Devices for Intel® Quartus® Prime Standard Edition Software
FPGA Used fMAX (MHz) Logic Size Architecture Performance
DMIPS/MHz Ratio CoreMark/MHz Ratio
Intel® Cyclone® IV E 81 4316 (LE) 0.942 1.49
Intel® Cyclone® V 117 1886 (ALM)
Intel® Arria® V 121 1917 (ALM)
Intel® Arria® V GZ 211 1859 (ALM)
Intel® Stratix® V 231 1853 (ALM)
Intel® Cyclone® 10 LP 93 4174 (LE)
Intel® Arria® 10 239 1818 (ALM)
Intel® MAX® 10 91 4199 (LE)
Table 70.  Benchmark Parameters for Intel® Quartus® Prime Standard Edition Software
Parameter Settings/Description
Intel® Quartus® Prime seed Maximum performance result are based on 10 seed sweep from Intel® Quartus® Prime Standard Edition software version 23.1.
Device speed grade Fastest speed grade from each Intel FPGA device family.
Defined peripherals
  • Nios® V/g processor core (without debug module, internal timer, floating point unit, 4 KB instruction cache, and 4 KB data cache).
  • 128 KB on-chip memory for the instruction and data bus.
  • JTAG UART Intel® FPGA IP.
  • Interval Timer Core.
Toolchain Version
  • riscv32-unknown-elf-gcc (GCC) version 12.1.0
  • CMake Version: 3.27.1
Compiler configuration
  • Compiler flags: -03
  • Assembler options: -Wa -gdwarf2
  • Compile options: -Wall -Wformat-security -march=rv32im_zicbom -mabi=ilp32

Intel uses the same Intel® Quartus® Prime design example for maximum performance benchmark(fMAX) and logic size benchmarks. The compiler settings are:

  • Superior Performance with Maximum Placement Effort in Intel® Quartus® Prime Pro Edition software.
  • High Performance Effort in Intel® Quartus® Prime Standard Edition software.
Note: Results may vary depending on the version of the Intel® Quartus® Prime software, the version of the Nios® V processor, compiler version, target device and the configuration of the processor. Additionally, any changes to the system logic design can change the performance and LE usage. All results are generated from design built with Platform Designer.