Nios® V Processor Reference Manual

ID 683632
Date 12/11/2023

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Document Table of Contents Cache Memory

The Nios® V/g processor architecture supports cache memories on both the instruction manager port (instruction cache) and the data manager port (data cache). The cache memories can improve the average memory access time for Nios® V/g processor systems that use slow off-chip memory such as SDRAM for programme and data storage.

The processor core connects the caches through a 32-bit AXI-4 interface, thus bursting is enabled. The instruction and data caches are always enabled at run-time, but software can bypass the data cache so that peripheral accesses do not return cached data. Software handles cache management and cache coherency. The Nios® V/g instruction set provides instructions for cache management.

Table 80.  Cache Byte Address Field
Bit Fields
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
tag tag/index index offset