The value in the each CSR registers determines the state of the Nios® V/m processor. The field descriptions are based on the RISC-V specification.
Table 19. Vendor ID Register FieldsThe mvendorid CSR is a 32-bit read-only register that provides the JEDEC manufacturer ID of the provider of the core.
Bit Field |
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
Bank |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
Bank |
Offset |
Table 20. Architecture ID Register FieldsThe marchid CSR is a 32-bit read-only register encoding the base microarchitecture of the hart.
Bit Field |
31 |
30 |
29 |
28 |
27 |
26 |
25 |
... |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
Architecture ID |
Table 21. Implementation ID Register FieldsThe mimpid CSR provides a unique encoding of the version of the processor implementation.
Bit Field |
31 |
30 |
29 |
28 |
27 |
26 |
25 |
... |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
Implementation |
Table 22. Hardware Thread ID Register FieldsThe mhartid CSR is a 32-bit read-only register that contains the integer ID of the hardware thread running the code
Bit Field |
31 |
30 |
29 |
28 |
27 |
26 |
25 |
... |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
Hart ID |
Table 23. Machine Status Register FieldsThe mstatus register is a 32-bit read-write register that keeps track of and controls the hart’s current operating state.
Bit Field |
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
SD |
WPRI |
TSR |
TW |
TVM |
MXR |
SUM |
MPRV |
XS[1:0] |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
XS[1:0] |
FS[1:0] |
MPP[1:0] |
WPRI |
SPP |
MPIE |
WPRI |
SPIE |
UPIE |
MIE |
WPRI |
SIE |
UIE |
Table 24. Machine ISA Register FieldsThe misa CSR is a read-write register reporting the ISA supported by the hart.
Bit Field |
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
MXL[1:0] |
WLRL |
Extension[25:0] |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
Extension[25:0] |
Table 25. Machine Interrupt-Enable Register FieldsThe mie register is a 32-bit read-write register that contains interrupt enable bits.
Bit Field |
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
WPRI |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
WPRI |
MEIE |
WPRI |
SEIE |
UEIE |
MTIE |
WPRI |
STIE |
UTIE |
MSIE |
WPRI |
SSIE |
USIE |
Table 26. Machine Trap-Handler Base Address Register FieldsThe mtvec register is a 32-bit read/write register that holds trap vector configuration, consisting of a vector base address (BASE) and a vector mode (MODE).
Bit Field |
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
Base[31:2] |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
Base[31:2] |
Mode |
Table 27. Machine Exception Program Counter Register FieldsThe mepc register is a 32-bit read-write register that holds the addresses of the instruction that was interrupted or that encountered the exception when a trap is taken into M-mode.
Bit Field |
31 |
30 |
29 |
28 |
27 |
26 |
25 |
... |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
mepc |
Table 28. Machine Trap Cause Register FieldsThe mcause register is a 32-bit read-write register that hold the code indicating the event that caused the trap when a trap is taken into M-mode.
Bit Field |
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
Interrupt |
Exception code [30:16] |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
Exception code [15:0] |
Table 29. Machine Trap Value Register Fields The mtval register is a 32-bit read-write register that is written with exception-specific information to assist software in handling the trap when a trap is taken into M-mode.
Bit Field |
31 |
30 |
29 |
28 |
27 |
26 |
25 |
... |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
mtval |
Table 30. Machine Interrupt-Pending Register FieldsThe mip register is a 32-bit read/write register containing information on pending interrupts.
Bit Field |
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
WPRI |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
WPRI |
MEIP |
WPRI |
SEIP |
UEIP |
MTIP |
WPRI |
STIP |
UTIP |
MSIP |
WPRI |
SSIP |
USIP |
Table 31. Trigger Select Register FieldsThe tselect register is a 32-bit read/write register that selects the current trigger is accessible by other trigger register.
Bit Field |
31 |
30 |
29 |
28 |
27 |
26 |
25 |
... |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
tselect |
Table 32. Trigger Data 1 (Match Control) Register FieldsThe tdata1 (mcontrol) register is a 32-bit read/write register containing information on the trigger type, tdata registers accessibility, and trigger implementation
Bit Field |
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
type=2 |
dmode |
maskmax |
hit |
select |
timing |
sizelo |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
action |
chain |
match |
m |
0 |
s |
u |
execute |
store |
load |
Table 33. Trigger Data 2 Register FieldsThe tdata2 register is a 32-bit read/write register containing the trigger-specific data.
Bit Field |
31 |
30 |
29 |
28 |
27 |
26 |
25 |
… |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
tdata2 |
Table 34. Trigger Info Register FieldsThe tinfo register is a 32-bit read-only register containing information on each possible tdata1.type.
Bit Field |
31 |
30 |
29 |
… |
18 |
17 |
16 |
15 |
14 |
13 |
… |
2 |
1 |
0 |
0 |
info |
Table 35. Debug Control and Status Register FieldsThe dcsr CSR is a 32-bit read-write register containing information and status during D-mode
Bit Field |
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
debugver |
0 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
ebreakm |
0 |
ebreaks |
ebreaku |
stepie |
stopcount |
stoptime |
cause |
0 |
mprven |
nmip |
step |
prv |
Table 36. Debug Program Counter Register FieldsUpon entry to D-mode, dpc CSR is updated with the virtual address of the next instruction to be executed.
Bit Field |
31 |
30 |
29 |
28 |
27 |
26 |
25 |
... |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
dpc |