Nios® V Processor Reference Manual

ID 683632
Date 5/26/2023
Document Table of Contents Abstract Commands in Debug Mode

Nios® V/g processor implements Access Register abstract command. The Access Register command allows read-write access to the processor registers including GPRs, CSRs, FP registers and Program Counter. The Access Register also allows program execution from program buffer. The debugger executes Access Register commands by writing into Abstract Command (command) register using the Access Register command encoding.

Table 60.  Access Register Command Encoding
Bit Field
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
cmdtype 0 aarsize aarpostincrement postexec transfer write
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Table 61.  Fields Descriptions
Field Role
cmdtype Determine command type

0 : Indicates Access Register command.

aarsize Specifies size of register access

2: Access the lowest 32 bit of register

3: Access the lowest 64 bit of register

4: Access the lowest 128 bit of register

aarpostincrement 0: No effect

1: regno is incremented after successful register access


0: No effect

1: Execute program in program buffer

Acts in conjunction with write field.

0: Ignore value in write field

1: Execute operation specified by write field.

0: Copy data from register

1: Copy data to register
regno Register address to be accessed.
Note: The Nios® V/g processor does not support abstract commands when hardware thread is not halted.
Table 62.  Software Response to Unimplemented Commands
Field State
cmderr[10:8] 0 No error
1 Busy
2 Command not supported
3 Exception - from program buffer instruction
4 Command not executed because hart unavailable, or not in correct state to execute command.
5 Abstract command failed due to bus error
7 Command failed for other reasons.
Debug Module has the Abstract Control and Status CSR which includes the cmderr field. The cmderr field represents the current state of abstract command being executed. If the cmderr field is non-zero, writes to the command register are ignored. To clear the cmderr field, write 1 for every bit in the field.
Figure 9. Debug Module Interface Signals

Avalon® memory-mapped interface implement the Register Access using request/response bus with Debug Module being the initiator and core being the responder. Address bus carries the register ID.

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