188.8.131.52.1. Instruction Cache
The instruction cache memory has the following characteristics:
- Direct-mapped cache implementation
- 32 bytes (8 words) per cache line
- Configurable size of 1, 2, 4, 8, and 16 KBytes
- The instruction manager port reads an entire cache line at a time from memory, and issues one read per clock cycle.
- Critical word first
The instruction byte address size is 32-bit. The size of the tag and index field depends only on the size of the cache memory. The offset field is always five bits (i.e., a 32-byte line). The instruction fetch fence (fence.i) instruction flushes and invalidates all instruction cache lines.
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