AN 777: Data Word Alignment Calibration With Multiple Intel FPGA PHYLite for Parallel Interfaces IP Cores

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ID 683631
Date 1/12/2018
Public
Document Table of Contents
Document Table of Contents x
1. AN 777: Data Word Alignment Calibration With Multiple Intel FPGA PHYLite for Parallel Interfaces IP Cores
1. AN 777: Data Word Alignment Calibration With Multiple Intel FPGA PHYLite for Parallel Interfaces IP Cores x
1.1. Features 1.2. Hardware and Software Requirements 1.3. Compiling the Reference Design 1.4. Hardware Setup 1.5. Generating Executable and Linking Format (.elf) Programming File 1.6. Running the Hardware Reference Design 1.7. Results 1.8. Reference Design Architecture 1.9. Document Revision History for AN 777: Data Word Alignment Calibration With Multiple Intel FPGA PHYLite for Parallel Interfaces IP Cores
1.7. Results x
1.7.1. Random Data Transfer Result 1.7.2. Dynamic Calibration Result
1.8. Reference Design Architecture x
1.8.1. Functional Description 1.8.2. Data Word Alignment Algorithm 1.8.3. Timing Analysis Guidelines Input Interface Delay Constraints Output Interface Delay Constraints
1. AN 777: Data Word Alignment Calibration With Multiple Intel FPGA PHYLite for Parallel Interfaces IP Cores

1.8.3. Timing Analysis Guidelines

The reference design uses the following timing analysis flow to obtain the accurate value for Input Strobe Setup Delay, Input Strobe Hold Delay Constraint, Output Strobe Setup Delay Constraint,, and Output Strobe Hold Delay Constraint to perform timing closure for both output and input interfaces.
Figure 19. Timing Analysis Flow

It is crucial to set the Input Strobe Setup Delay, Input Strobe Hold Delay Constraint, Output Strobe Setup Delay Constraint, and Output Strobe Hold Delay Constraint for both dut_INPUT and dut_OUTPUT module to 0 initially to eliminate unnecessary interface constraints. The phylite_interface_constraints.tcl script then automatically calculates the TcoMax and TcoMin values for input interface delay constraints and Tsu and Th values for output interface delay constraints.

The TimeQuest Analyzer generates a report based on the calculations performed by the script.

Figure 20. PHYLite Interface Constraints Report

Input Interface Delay Constraints

Use the TcoMax value to calculate the Input Strobe Setup Delay Constraint and TcoMin value to calculate the Input Strobe Hold Delay Constraint. The input interface delay constraints must include board skew to perform accurate timing analysis.

Input Strobe Setup Delay Constraint = TcoMax + board skew

Input Strobe Hold Delay Constraint = TcoMin + board skew

Update the new Input Strobe Setup Delay Constraint and Input Strobe Hold Delay Constraint values to the dut_INPUT module and re-compile the design.

Figure 21. Calculated Input Interface Delay Constraints

Output Interface Delay Constraints

Use the Tsu value to calcuate the Output Strobe Setup Delay Constraint and Th value to calculate Output Strobe Hold Delay Constraint. The output interface delay constraints must include board skew to perform accurate timing analysis.

Output Strobe Setup Delay Constraint = Tsu + board skew

Output Strobe Hold Delay Constraint = Th - board skew

Update the new Output Strobe Setup Delay Constraint and Output Strobe Hold Delay Constraint values to the dut_OUTPUT module and re-compile the design.

Figure 22. Calculated Output Interface Delay Constraints
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