1.8.1. Functional Description
This module takes the input from Si570 Programmable Oscillator and provides reference clock to the internal PLL modules in each of the Intel FPGA PHYLite for Parallel Interfaces IP cores.
This Intel FPGA PHYLite for Parallel Interfaces IP core transfers data from ATSO_DYN_CFG_CTRL or traffic generator module to dut_INPUT module. During configuration and calibration mode, this module takes data from ATSO_DYN_CFG_CTRL module and send to dut_INPUT module. In normal operating mode, this module takes data from traffic generator and sends to dut_INPUT module.
This Intel FPGA PHYLite for Parallel Interfaces IP core receives data from dut_OUTPUT module. This module sends the received data to ATSO_DYN_CFG_CTRL module during configuration and calibration mode, and to traffic generator during normal operating mode for data verification.
The Avalon controller is responsible to perform address translation to retrieve the physical address of the strobe and data pins and sends reconfiguration commands to dut_OUTPUT module.
ATSO_DYN_CFG_CTRL with Nios II Processor Module
|Parallel I/O Module||Address Map||Description|
|phy_write_data||0x20||Sends calibration test data to dut_OUTPUT module.|
|phy_write_ctrl||0x30||Asserts rdata_en signal during calibration mode.|
|phy_read_data||0x40||Receives data from dut_INPUT module for comparison against test data.|
|phy_read_status||0x50||Receives rdata_valid signal from dut_INPUT module.|
|cal_mode||0x60||Asserts cfg_done signal to exit calibration mode and activates traffic generator module for data transfer for normal operating mode.|
Traffic Generator Module
Traffic Generator module is responsible for transmitting data to dut_OUTPUT and receiving data from dut_INPUT during normal operating mode. The module uses Linear Feedback Shift Register (LFSR) to generate random data for transmission. Traffic generator performs data comparison to the received data to ensure the strobe enable delay setting is configured correctly.