AN 777: Data Word Alignment Calibration With Multiple Intel FPGA PHYLite for Parallel Interfaces IP Cores

ID 683631
Date 1/12/2018

1.3. Compiling the Reference Design

  1. Follow the guidelines in Getting Started with the Design Store to download and install the reference design files.
  2. Open the reference design .qpf file after successfully installing the design templates.
  3. In the Intel® Quartus® Prime software, open dut_INPUT.qsys and dut_OUTPUT.qsys files. Make sure the Intel FPGA PHYLite IP core has the same configurations shown below:
    Figure 1.  General Tab Configuration for dut_INPUT Module
    Figure 2.  Group 0 Tab Configuration for dut_INPUT Module
    Figure 3.  General Tab Configuration for dut_OUTPUT Module
    Figure 4.  Group 0 Tab Configuration for dut_OUTPUT Module
  4. In Intel® Quartus® Prime software, click on Assignments > Settings > TimeQuest Timing Analyzer.
  5. In the Tcl Script File name, type in phylite_interface_constraints.tcl and select Run default timing analysis before running customer script.
    Figure 5. Adding Interface Constraints Calculation Script
  6. Click Apply and OK.
  7. In the Intel® Quartus® Prime, click Processing > Start Compilation to compile the reference design.

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