AN 777: Data Word Alignment Calibration With Multiple Intel FPGA PHYLite for Parallel Interfaces IP Cores

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ID 683631
Date 1/12/2018
Public
Document Table of Contents
Document Table of Contents x
1. AN 777: Data Word Alignment Calibration With Multiple Intel FPGA PHYLite for Parallel Interfaces IP Cores
1. AN 777: Data Word Alignment Calibration With Multiple Intel FPGA PHYLite for Parallel Interfaces IP Cores x
1.1. Features 1.2. Hardware and Software Requirements 1.3. Compiling the Reference Design 1.4. Hardware Setup 1.5. Generating Executable and Linking Format (.elf) Programming File 1.6. Running the Hardware Reference Design 1.7. Results 1.8. Reference Design Architecture 1.9. Document Revision History for AN 777: Data Word Alignment Calibration With Multiple Intel FPGA PHYLite for Parallel Interfaces IP Cores
1.7. Results x
1.7.1. Random Data Transfer Result 1.7.2. Dynamic Calibration Result
1.8. Reference Design Architecture x
1.8.1. Functional Description 1.8.2. Data Word Alignment Algorithm 1.8.3. Timing Analysis Guidelines
1. AN 777: Data Word Alignment Calibration With Multiple Intel FPGA PHYLite for Parallel Interfaces IP Cores

1.3. Compiling the Reference Design

  1. Follow the guidelines in Getting Started with the Design Store to download and install the reference design files.
  2. Open the reference design .qpf file after successfully installing the design templates.
  3. In the Intel® Quartus® Prime software, open dut_INPUT.qsys and dut_OUTPUT.qsys files. Make sure the Intel FPGA PHYLite IP core has the same configurations shown below:
    Figure 1.  General Tab Configuration for dut_INPUT Module
    Figure 2.  Group 0 Tab Configuration for dut_INPUT Module
    Figure 3.  General Tab Configuration for dut_OUTPUT Module
    Figure 4.  Group 0 Tab Configuration for dut_OUTPUT Module
  4. In Intel® Quartus® Prime software, click on Assignments > Settings > TimeQuest Timing Analyzer.
  5. In the Tcl Script File name, type in phylite_interface_constraints.tcl and select Run default timing analysis before running customer script.
    Figure 5. Adding Interface Constraints Calculation Script
  6. Click Apply and OK.
  7. In the Intel® Quartus® Prime, click Processing > Start Compilation to compile the reference design.
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