AN 686: Implementing 9.8 Gbps CPRI in Arria V GT and ST Devices

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ID 683613
Date 12/06/2013
Public
Document Table of Contents
Document Table of Contents x
1. Implementing 9.8G CPRI in Arria V GT and ST FPGAs
1. Implementing 9.8G CPRI in Arria V GT and ST FPGAs x
1.1. Native PHY IP Settings in PMA Direct Mode 1.2. Soft PCS Architecture 1.3. Soft PCS Clocking 1.4. Soft PCS Latency 1.5. Auto Rate Negotiation 1.6. Soft PCS Parameters and Ports 1.7. Document Revision History
1.2. Soft PCS Architecture x
1.2.1. Transmit and Receive Registers 1.2.2. Transmit and Receive Width Adapters 1.2.3. Phase Measuring FIFO
1.5. Auto Rate Negotiation x
1.5.1. CMU PLL Optimization 1.5.2. Configurations 1.5.3. Steps for Auto Rate Negotiation
1. Implementing 9.8G CPRI in Arria V GT and ST FPGAs

1.2.1. Transmit and Receive Registers

The transmit and receive registers synchronize the data from the core or PMA with the soft PCS clocks. The reset signal is synchronized with the usr_clk before it is fed to all the blocks. The functionality of the 8b/10b encoder and decoder, the TX Bitslip, and Word Aligner is identical to those in the hard PCS. The word aligner outputs the number of bits slipped on its rx_boundary_sel output port.

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