AN 686: Implementing 9.8 Gbps CPRI in Arria V GT and ST Devices

ID 683613
Date 12/06/2013

1.2.1. Transmit and Receive Registers

The transmit and receive registers synchronize the data from the core or PMA with the soft PCS clocks. The reset signal is synchronized with the usr_clk before it is fed to all the blocks. The functionality of the 8b/10b encoder and decoder, the TX Bitslip, and Word Aligner is identical to those in the hard PCS. The word aligner outputs the number of bits slipped on its rx_boundary_sel output port.