AN 686: Implementing 9.8 Gbps CPRI in Arria V GT and ST Devices

ID 683613
Date 12/06/2013

1.2.3. Phase Measuring FIFO

The phase measuring FIFO transfers the data from the write clock domain to the read clock domain. For example, in the TX path it transfers the data from usr_pma_clk clock domain to tx_pma_clk clock domain and similarly, for the RX path it transfers the data from rx_pma_clk clock domain to usr_pma_clk clock domain. The FIFO calculates the phase difference between the read and write clock domains as well as the number of data bits stored in the FIFO for latency calculation.

You can measure the FIFO latency to the desired precision using the dedicated fifo_calc_clk clock signal. The frequency of fifo_calc_clk is related to the usr_pma_clk period. N clock periods of the fifo_calc_clk are equal to M clock periods of usr_pma_clk where N and M are integers. For example, N may be multiple of M, or based on the required accuracy the ratio of M/N may be greater than 1 ( such as 64/63 or 128/127). The accuracy for measuring the FIFO latency using the fifo_calc_clk signal increases as the M/N ratio approaches 1. For the TX and RX phase measuring FIFOs, set the value of N using the tx_fifo_sample_size and rx_fifo_sample_size input ports respectively.

The accuracy for measuring the FIFO latency is N/(least common multiple of usr_pma_clk periods). The FIFO latency can be read from the fifo_latency port.

Note: If your application does not require high precision, drive the fifo_calc_clk input port with the usr_pma_clk signal. In this case, the M/N ratio is 1 because the frequencies are the same. You can also connect the fifo_calc_clk signal to logic 0.

The accumulated phase difference measured across the sample size of N clock periods can be accessed through phase_measure_acc port. The ph_acc_valid port indicates that the phase_measure_acc port is updated with the new data in fifo_calc_clk domain.