AN 686: Implementing 9.8 Gbps CPRI in Arria V GT and ST Devices

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ID 683613
Date 12/06/2013
Public
Document Table of Contents
Document Table of Contents x
1. Implementing 9.8G CPRI in Arria V GT and ST FPGAs
1. Implementing 9.8G CPRI in Arria V GT and ST FPGAs x
1.1. Native PHY IP Settings in PMA Direct Mode 1.2. Soft PCS Architecture 1.3. Soft PCS Clocking 1.4. Soft PCS Latency 1.5. Auto Rate Negotiation 1.6. Soft PCS Parameters and Ports 1.7. Document Revision History
1.2. Soft PCS Architecture x
1.2.1. Transmit and Receive Registers 1.2.2. Transmit and Receive Width Adapters 1.2.3. Phase Measuring FIFO
1.5. Auto Rate Negotiation x
1.5.1. CMU PLL Optimization 1.5.2. Configurations 1.5.3. Steps for Auto Rate Negotiation
1. Implementing 9.8G CPRI in Arria V GT and ST FPGAs

1. Implementing 9.8G CPRI in Arria V GT and ST FPGAs

This application note describes the implementation of 9.8304 Gbps Common Public Radio Interface (CPRI) using the Arria® V GT and Arria® V ST FPGA transceivers.

The hard physical coding sublayer (PCS) block in Arria V FPGAs supports data rates up to 6.5536 Gbps. To implement 9.8304 Gbps CPRI, the transceiver is configured in Physical Media Attachment (PMA) direct mode and a soft PCS block is implemented in the FPGA core.

The following sections describe the configuration of Native PHY IP in PMA direct mode, the architecture of the soft PCS in the FPGA core, and the steps for auto rate negotiation from 9.8304 Gbps down to 1.2288 Gbps.

Note: This application note is accompanied by a reference design to demonstrate the soft PCS implementation and auto rate negotiation from 9.8304 Gbps down to 1.2288 Gbps.

Section Content
Native PHY IP Settings in PMA Direct Mode
Soft PCS Architecture
Soft PCS Clocking
Soft PCS Latency
Auto Rate Negotiation
Soft PCS Parameters and Ports
Document Revision History

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