AN 686: Implementing 9.8 Gbps CPRI in Arria V GT and ST Devices

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ID 683613
Date 12/06/2013
Public
Document Table of Contents
Document Table of Contents x
1. Implementing 9.8G CPRI in Arria V GT and ST FPGAs
1. Implementing 9.8G CPRI in Arria V GT and ST FPGAs x
1.1. Native PHY IP Settings in PMA Direct Mode 1.2. Soft PCS Architecture 1.3. Soft PCS Clocking 1.4. Soft PCS Latency 1.5. Auto Rate Negotiation 1.6. Soft PCS Parameters and Ports 1.7. Document Revision History
1.2. Soft PCS Architecture x
1.2.1. Transmit and Receive Registers 1.2.2. Transmit and Receive Width Adapters 1.2.3. Phase Measuring FIFO
1.5. Auto Rate Negotiation x
1.5.1. CMU PLL Optimization 1.5.2. Configurations 1.5.3. Steps for Auto Rate Negotiation
1. Implementing 9.8G CPRI in Arria V GT and ST FPGAs

1.2. Soft PCS Architecture

The soft PCS is implemented in the FPGA core and is connected to the transceiver PMA through the 80-bit interface. The input data width to the transmit and receive registers is 32 bits when 8b/10b encoding is enabled and 40 bits when 8b/10b encoding is disabled.

Figure 3. Soft PCS Architecture for Data Rates from 4.9152 Gbps to 9.8304 Gbps


Note: The PMA interface width is 80 bits for data rates of 4.9152 Gbps and above.
Figure 4. Soft PCS Architecture for Data Rates from 1.2288 Gbps to 3.072 Gbps


Note: The PMA interface width is 20 bits for data rates of 3.072 Gbps and below.

Section Content
Transmit and Receive Registers
Transmit and Receive Width Adapters
Phase Measuring FIFO

Level Two Title