1.2. Soft PCS Architecture
The soft PCS is implemented in the FPGA core and is connected to the transceiver PMA through the 80-bit interface. The input data width to the transmit and receive registers is 32 bits when 8b/10b encoding is enabled and 40 bits when 8b/10b encoding is disabled.
Figure 3. Soft PCS Architecture for Data Rates from 4.9152 Gbps to 9.8304 Gbps
Note: The PMA interface width is 80 bits for data rates of 4.9152 Gbps and above.
Figure 4. Soft PCS Architecture for Data Rates from 1.2288 Gbps to 3.072 Gbps
Note: The PMA interface width is 20 bits for data rates of 3.072 Gbps and below.
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