AN 686: Implementing 9.8 Gbps CPRI in Arria V GT and ST Devices

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ID 683613
Date 12/06/2013
Public
Document Table of Contents
Document Table of Contents x
1. Implementing 9.8G CPRI in Arria V GT and ST FPGAs
1. Implementing 9.8G CPRI in Arria V GT and ST FPGAs x
1.1. Native PHY IP Settings in PMA Direct Mode 1.2. Soft PCS Architecture 1.3. Soft PCS Clocking 1.4. Soft PCS Latency 1.5. Auto Rate Negotiation 1.6. Soft PCS Parameters and Ports 1.7. Document Revision History
1.2. Soft PCS Architecture x
1.2.1. Transmit and Receive Registers 1.2.2. Transmit and Receive Width Adapters 1.2.3. Phase Measuring FIFO
1.5. Auto Rate Negotiation x
1.5.1. CMU PLL Optimization 1.5.2. Configurations Soft PCS Configuration fPLL Configuration 1.5.3. Steps for Auto Rate Negotiation
1. Implementing 9.8G CPRI in Arria V GT and ST FPGAs

1.5.2. Configurations

Soft PCS Configuration

Use the following configuration settings for soft PCS and fPLL:

  • Set data rate to 9.8304 Gbps.
  • Set the transmit PLL reference clock to 122.88 MHz.
  • Set data_width_pma port to 7'd80.

fPLL Configuration

  • Set fPLL reference clock to 122.88 MHz
  • Set 2 different output clocks.
  • Set Output clock 0 as usr_clk at 245.76 MHz and set output clock 1 as usr_pma_clk at 122.88 MHz.

Perform channel reconfiguration to switch between TX PLL 0 and TX PLL1, to change the local clock divider factor, and to change the CDR PLL settings.

Level Two Title