AN 686: Implementing 9.8 Gbps CPRI in Arria V GT and ST Devices

ID 683613
Date 12/06/2013

1.5.2. Configurations

Soft PCS Configuration

Use the following configuration settings for soft PCS and fPLL:

  • Set data rate to 9.8304 Gbps.
  • Set the transmit PLL reference clock to 122.88 MHz.
  • Set data_width_pma port to 7'd80.

fPLL Configuration

  • Set fPLL reference clock to 122.88 MHz
  • Set 2 different output clocks.
  • Set Output clock 0 as usr_clk at 245.76 MHz and set output clock 1 as usr_pma_clk at 122.88 MHz.

Perform channel reconfiguration to switch between TX PLL 0 and TX PLL1, to change the local clock divider factor, and to change the CDR PLL settings.