AN 686: Implementing 9.8 Gbps CPRI in Arria V GT and ST Devices

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ID 683613
Date 12/06/2013
Public
Document Table of Contents
Document Table of Contents x
1. Implementing 9.8G CPRI in Arria V GT and ST FPGAs
1. Implementing 9.8G CPRI in Arria V GT and ST FPGAs x
1.1. Native PHY IP Settings in PMA Direct Mode 1.2. Soft PCS Architecture 1.3. Soft PCS Clocking 1.4. Soft PCS Latency 1.5. Auto Rate Negotiation 1.6. Soft PCS Parameters and Ports 1.7. Document Revision History
1.2. Soft PCS Architecture x
1.2.1. Transmit and Receive Registers 1.2.2. Transmit and Receive Width Adapters 1.2.3. Phase Measuring FIFO
1.5. Auto Rate Negotiation x
1.5.1. CMU PLL Optimization 1.5.2. Configurations 1.5.3. Steps for Auto Rate Negotiation
1. Implementing 9.8G CPRI in Arria V GT and ST FPGAs

1.6. Soft PCS Parameters and Ports

Most of the parameters and ports for the soft PCS are identical to hard PCS, except for the parameters and ports for the phase measuring FIFO which do not exist in the hard PCS.
Table 4.  Soft PCS Parameters
Name Type Default Value Description
operation_mode String Duplex Defines the mode in which the transceiver channel is instantiated.
lanes Integer 1 Sets the number of transceiver channels in the design. In the attached reference design, it is set to one.
ser_base_factor Integer 8 Enables or disables the 8B/10B encoder and decoder within the soft PCS. To bypass the 8B/10B logic within the soft PCS, set this parameter's value to 10.
ser_words Integer 4 Determines the data width from the upper layer. Data_width = (ser_base_factor * ser_words). Set this value to 4.
pcs_pma_width Integer 80 Determines the PCS to PMA interface data width. For 9.8 Gbps data rate, data width must be 80 bits.
ser_word_pma_size Integer 4 The value is ceil[log2(number of 8-bit data on PCS to PMA interface)]. In this case, the PCS to PMA interface data width is 80 and the number of 8-bit data is 10. Ceil[log2(10)] is 4.
data_width_pma_size Integer 7 The value is ceil[log2(PCS to PMA interface data width)]. The PCS to PMA interface data width is 80 bits. Ceil[log2(80)] is 7.
base_data_rate String 0 Mbps Determines the clock generation block (CGB) factor. Can be ignored for 9.8 Gbps data rate.
tx_pma_clk_div Integer 1 Determines the clock generation block (CGB) division factor. Can be ignored for 9.8 Gbps data rate.
pll_feedback_path String No compensation Disables the PLL feedback path. Because the phase measuring FIFO is in the soft PCS, disable the PLL feedback path.
word_aligner_mode String Deterministic Latency Determines the word aligner's mode of operation.
pll_refclk_cnt Integer 1 Specifies the number of reference clocks for the PLL. Match the number of reference clocks for the PLL with the Native PHY IP instance.
plls Integer 2 Specifies the number of TX PLLs in the design. For auto rate negotiation from 9.8304 Gbps to 1.2288 Gbps set the
cdr_refclk_cnt Integer 1 Specifies the number of reference clocks for the CDR. Match the number of reference clocks for the CDR with the Native PHY IP instance.
tx_fifo_depth Integer 4 Determines the depth of the transmit phase measuring FIFO. The value is log2(FIFO buffer depth). In this case, the FIFO buffer depth is 16 and the value of log2(16) is 4.
rx_fifo_depth Integer 4 Determines the depth of the receive phase measuring FIFO. The value is log2(FIFO buffer depth). In this case, the FIFO buffer depth is 16 and the value of log2(16) is 4.
ref_design Integer 1 Set this value to 1 if you choose to use the IP as a reference design.
Table 5.  Soft PCS Ports
Signal Name Direction Description
usr_clk Input Clocks the 32-bit data from the upper layer to the soft PCS.
usr_pma_clk Input Clocks the soft PCS data before transferring to the tx_pma_clk or rx_pma_clk domain through the phase measuring FIFO.
fifo_calc_clk Input Clocks the phase measuring FIFO to calculate the phase difference between the write clock and read clock of the phase measuring FIFO.
cdr_ref_clk Input Input reference clock for the CDR.
tx_fifo_sample_size Input

Value to determine fifo_calc_clk frequency. User-defined value N where M/N=fifo_calc_clk period/usr_pma_clk period. Synchronize internally to fifo_calc_clk. Set the value of N using the tx_fifo_sample_size input port.

rx_fifo_sample_size Input

Value to determine fifo_calc_clk frequency. Sample size for calculating the phase difference in the RX phase measuring FIFO. User-defined value N where M/N=fifo_calc_clk period/usr_pma_clk period. Synchronize internally to fifo_calc_clk. Set the value of N using the rx_fifo_sample_size input port.

tx_phase_measure_acc Output Measures the accumulated delay through the transmit buffer in fifo_calc_clk clock domain.
rx_phase_measure_acc Output Measures the accumulated delay through the receive buffer in fifo_calc_clk clock domain.
tx_fifo_latency Output Latency of TX phase measuring FIFO buffer in usr_pma_clk domain.
rx_fifo_latency Output Latency of RX phase measuring FIFO buffer in usr_pma_clk domain.
tx_ph_acc_valid Output Indicates that the phase_measure_acc port for RX phase measuring FIFO contains updated data in fifo_calc_clk domain.
rx_ph_acc_valid Output Indicates that the phase_measure_acc port for the RX phase measuring FIFO contains updated data in fifo_calc_clk clock domain.
tx_wr_full Output Indicates that the TX phase measuring FIFO in usr_pma_clk clock domain is full.
rx_wr_full Output Indicates that the RX phase measuring FIFO in rx_pma_clk clock domain is full.
tx_rd_empty Output Indicates that the TX phase measuring FIFO in tx_pma_clk clock domain is empty.
rx_rd_empty Output Indicates that the RX phase measuring FIFO in usr_pma_clk clock domain is empty.
data_width_pma Input Specifies the effective PMA width used during that period.
error Output Indicates that the value for data_width_pma is invalid.
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