AN 686: Implementing 9.8 Gbps CPRI in Arria V GT and ST Devices

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ID 683613
Date 12/06/2013
Public
Document Table of Contents
Document Table of Contents x
1. Implementing 9.8G CPRI in Arria V GT and ST FPGAs
1. Implementing 9.8G CPRI in Arria V GT and ST FPGAs x
1.1. Native PHY IP Settings in PMA Direct Mode 1.2. Soft PCS Architecture 1.3. Soft PCS Clocking 1.4. Soft PCS Latency 1.5. Auto Rate Negotiation 1.6. Soft PCS Parameters and Ports 1.7. Document Revision History
1.2. Soft PCS Architecture x
1.2.1. Transmit and Receive Registers 1.2.2. Transmit and Receive Width Adapters 1.2.3. Phase Measuring FIFO
1.5. Auto Rate Negotiation x
1.5.1. CMU PLL Optimization 1.5.2. Configurations 1.5.3. Steps for Auto Rate Negotiation
1. Implementing 9.8G CPRI in Arria V GT and ST FPGAs

1.5.1. CMU PLL Optimization

To minimize the CMU PLL usage, choose a common appropriate base data rate. To achieve the desired effective data rate, use the local clock divider block. Two CMU PLLs are required to support multiple CPRI channels which require auto rate negotiation independently within the range from 9.8304 Gbps to 1.2288 Gbps.

Figure 6. CMU PLL Optimization and Channel UtilizationThe following figure shows the four CPRI channels that are required to change the data rate by performing CMU PLL switching and channel reconfiguration.


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