AN 686: Implementing 9.8 Gbps CPRI in Arria V GT and ST Devices

ID 683613
Date 12/06/2013

1.5.1. CMU PLL Optimization

To minimize the CMU PLL usage, choose a common appropriate base data rate. To achieve the desired effective data rate, use the local clock divider block. Two CMU PLLs are required to support multiple CPRI channels which require auto rate negotiation independently within the range from 9.8304 Gbps to 1.2288 Gbps.

Figure 6. CMU PLL Optimization and Channel UtilizationThe following figure shows the four CPRI channels that are required to change the data rate by performing CMU PLL switching and channel reconfiguration.