Visible to Intel only — GUID: mwh1409959440867
Ixiasoft
Visible to Intel only — GUID: mwh1409959440867
Ixiasoft
6.9. Avalon® Streaming Pipeline Stage Intel® FPGA IP
If the pipeline stage receives back pressure on its source interface, the pipeline stage continues to assert its source interface's current data output. While the pipeline stage is receiving back pressure on its source interface, and then receives new data on its sink interface, the pipeline stage internally buffers the new data. It then asserts back pressure on its sink interface.
After the backpressure is deasserted, the pipeline stage's source interface is deasserted and the pipeline stage asserts internally buffered data (if present). Additionally, the pipeline stage deasserts back pressure on its sink interface.