Intel® Quartus® Prime Pro Edition User Guide: Platform Designer

ID 683609
Date 12/20/2023
Public

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Document Table of Contents

1.9. Correcting Platform Designer System Timing Issues

You can help alleviate Platform Designer system timing issues by adjusting the following interconnect parameters on the Domains tab:
  • Limit interconnect pipeline stages to—increase the use of interconnect pipeline stages in each command and response path by increasing the value of this option up to 4. Platform Designer can insert up to four pipeline stages, depending on availability of pipeline locations, at the possible expense of additional latency and area. The default value is 1 pipeline stage.
  • Burst adapter implementation—enable the HiConnect converter (Improved timing and area) or Per-burst-type HiConnect converter (faster, higher area) implementation to control incoming bursts with optimized burst adapters. These settings produce an adapter that has improved timing, but may require more device resources for implementation.
  • Width adapter implementation—enable the Optimized converter (faster, higher area) implementation to control width adaptation with a particular converter. This setting produces an adapter that has higher fMAX, but requires more device resources for implementation.
Figure 64. Correcting Platform Designer System Timing Issues with Domains Tab Settings
Note: To manually add pipeline stages to the interconnect schematic, refer to Add Pipeline Stages to the Interconnect Schematic.