Intel® Quartus® Prime Pro Edition User Guide: Platform Designer

ID 683609
Date 12/20/2023
Public

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents

5.15.15. Avalon® Tristate Conduit Signal Roles

The following table lists the signal defined for the Avalon® Tristate Conduit interface. All Avalon® -TC signals apply to both hosts and agents and have the same meaning for both.
Table 118.  Tristate Conduit Interface Signal Roles
Signal Role Width Direction Required Description
request 1 Host → Agent Yes The meaning of request depends on the state of the grant signal, as the following rules dictate.

When request is asserted and grant is deasserted, request is requesting access for the current cycle.

When request is asserted and grant is asserted, request is requesting access for the next cycle. Consequently, request should be deasserted on the final cycle of an access.

The request signal deasserts in the last cycle of a bus access. The request signal can reassert immediately following the final cycle of a transfer. This protocol makes both rearbitration and continuous bus access possible if no other hosts are requesting access.

Once asserted, request must remain asserted until granted. Consequently, the shortest bus access is 2 cycles. Refer to Tristate Conduit Arbitration Timing for an example of arbitration timing.

grant 1 Agent → Host Yes When asserted, indicates that a tristate conduit host has access to perform transactions. The grant signal asserts in response to the request signal. The grant signal remains asserted until 1 cycle following the deassertion of request.
<name>_in 1 – 1024 Agent → Host No The input signal of a logical tristate signal.
<name>_out 1 – 1024 Host → Agent No The output signal of a logical tristate signal.
<name>_outen 1 Host → Agent No The output enable for a logical tristate signal.