Intel® Quartus® Prime Pro Edition User Guide: Platform Designer

ID 683609
Date 6/26/2023
Public

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6.1.4.3. Wait State Insertion

Wait states extend the duration of a transfer by one or more cycles. Wait state insertion logic accommodates the timing needs of each agent, and causes the host to wait until the agent can proceed. Platform Designer interconnect inserts wait states into a transfer when the target agent cannot respond in a single clock cycle, as well as in cases when agent read and write signals have setup or hold time requirements.

Wait state insertion logic is a small finite‑state machine that translates control signal sequencing between the agent side and the host side. Platform Designer interconnect can force a host to wait for the wait state needs of an agent; for example, arbitration logic in a multi-host system. Platform Designer generates wait state insertion logic based on the properties of all agents in the system.

Figure 186. Wait State Insertion Logic for One Host and One Agent