Intel® Quartus® Prime Pro Edition User Guide: Platform Designer

ID 683609
Date 6/26/2023
Public

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7.3.1. Generic Tri-State Controller Intel® FPGA IP

The Generic Tri-State Controller Intel® FPGA IP provides a template for a controller. You can customize the Generic Tri-State Controller with various parameters to reflect the behavior of an off-chip device. The following types of parameters are available for the Generic Tri-State Controller:
  • Width of the address and data signals
  • Read and write wait times
  • Bus turnaround time
  • Data hold time
Note: In calculating delays, the Generic Tri-State Controller chooses the larger of the bus turnaround time and read latency. Turnaround time is measured from the time that a command is accepted, not from the time that the previous read returned data.

The Generic Tri-State Controller includes the following interfaces:

  • Memory-mapped agent interface—This interface connects to a memory-mapped host, such as a processor.
  • Tristate Conduit Host interface—The tri-state host interface usually connects to the tri-state conduit agent interface of the tri-state conduit pin sharer.
  • Clock sink—The component’s clock reference. You must connect this interface to a clock source.
  • Reset sink—This interface connects to a reset source interface.