Intel® Quartus® Prime Pro Edition User Guide: Platform Designer

ID 683609
Date 6/26/2023
Public

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Document Table of Contents

6.10.1.1. Read and Write Address Channels

Most signals are allowed. However, the following limitations are present in Platform Designer 14.0:

  • Supports 64-bit addressing.
  • ID width limited to 18-bits.
  • HPS-FPGA host interface has a 12-bit ID.