Intel® Quartus® Prime Pro Edition User Guide: Platform Designer

ID 683609
Date 6/26/2023
Public

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7.12. Platform Designer System Design Components Revision History

The following revision history applies to this chapter:

Document Version Intel® Quartus® Prime Version Changes
2023.04.03 23.1
  • Added note about no support for fixed-latency pipelined read transfers to Avalon® Memory Mapped Pipeline Bridge Intel® FPGA IP topic.
  • The product family name is updated to "Intel Agilex 7" to reflect the different family members.
2022.09.26 22.3
  • Revised note about the default agent selection to Designating a Default Agent topic.
  • Revised note about the default agent selection to Specifying a Default Avalon Agent or AXI Subordinate topic.
  • Revised note about the default agent selection to Accessing Undefined Memory Regions topic.
2022.04.02 22.1
  • Updated entire chapter for new AXI "manager" and AXI "subordinate" replacement terms. Refer to the AMBA® AXI and ACE Protocol Specification.
  • Updated AXI Timeout Bridge Stages and AXI Timeout Bridge Parameters topics for new CSR behavior and parameters.
  • Updated the Avalon® Streaming Single-Clock and Dual-Clock FIFO IP Parameters topic for Pipeline pointers parameter.
2021.03.29 21.1
  • Converted to "host" and "agent" inclusive terminology for Avalon® memory mapped interface descriptions and related GUI elements throughout.
2021.01.14 20.4
  • Added descriptions to CSR Interrupt Status Information for the AXI Timeout Bridge table.
2019.11.11 19.1
  • Updated the names of Intel® FPGA IP components throughout.
  • Updated name of Test Pattern Checker IP to Avalon® Data Pattern Checker IP throughout.
  • Updated Address Span Extender figure bit order.
  • Provided directory path in Test Pattern Generator
2018.12.15 18.1
  • Replaced references to System Contents tab with new System View tab.
2017.11.06 17.1
  • Changed instances of Qsys Pro to Platform Designer .
  • Changed instances of AXI Default Slave to Error Response Slave.
  • Updated topics: Error Response Slave.
  • Updated Figure: Error Response Slave Parameter Editor.
  • Added Figure: Error Response Slave Parameter Editor with Enabled CSR Support.
  • Updated topics: CSR Registers and renamed to Error Response Slave CSR Registers.
  • Added topic: Error Response Slave Access Violation Service.
2016.10.31 16.1
  • Implemented Intel rebranding.
  • Implemented Qsys rebranding.
2016.05.03 16.0
Updated Address Span Extender
  • Address Span Extender register mapping better explained
  • Address Span Extender Parameters table added
  • Address Span Extender example added
2015.11.02 15.1 Changed instances of Quartus II to Quartus Prime.
2015.05.04 15.0 Avalon Memory Mapped Unaligned Burst Expansion Bridge and Avalon Memory Mapped Pipeline Bridge, Maximum pending read transactions parameter. Extended description.
December 2014 14.1
  • AXI Timeout Bridge.
  • Added notes to Avalon Memory Mapped Clock Crossing Bridge pertaining to:
    • SDC constraints for its internal asynchronous FIFOs.
    • FIFO-based clock crossing.
June 2014 14.0
  • AXI Bridge support.
  • Address Span Extender updates.
  • Avalon Memory Mapped Unaligned Burst Expansion Bridge support.
November 2013 13.1
  • Address Span Extender
May 2013 13.0
  • Added Streaming Pipeline Stage support.
  • Added AMBA APB support.
November 2012 12.1
  • Moved relevant content from the Embedded Peripherals IP User Guide.