Intel® Quartus® Prime Pro Edition User Guide: Platform Designer

ID 683609
Date 6/26/2023
Public

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents

4.4.4.2. Compile High Level Synthesis Files

The Compile option for High Level Synthesis (HLS) component instantiation in Platform Designer invokes the Intel HLS Compiler to compile HLS files and modify a generic component.
Performing a compile on an HLS file has the following results:
  • Imports an .ip resulting from the HLS compilation to the component name defined in the HLS file.
  • Sets the HDL entity name and HDL compilation library to the component defined in the HLS file.
  • Adds the .ip file to the empty generic component.
  • Adds paths to the .ip and _hw.tcl output files to the Platform Designer search path to enable instantiation.
  • Populates the signals and interfaces of the component from the .ip file.

After you have added an HLS file:

  1. Click Compile.
    Figure 131. HLS Component Instantiation
  2. In the HLS Options dialog box, you can select from the following options:
    Figure 132. HLS Options Dialog Box
    1. The project name defaults to the entity name defined in the HLS file. To set a new project name, select new project name and enter a new HLS project name in the dialog box.
      Figure 133. Change the Project Name
    2. Provide additional arguments to the HLS compiler. Refer to Command Compiler Options in the Intel High Level Synthesis Reference Manual for information on compiler arguments.
    3. Disable or enable simulation file creation.
      A simulation file is required to use the Run Verification option after compilation is complete.
    4. Enable verbose logging to create a compilation log file.
    5. Enable or disable display of the HLS report in a browser window directly after compilation is complete.
    6. Perform verification with or without additional verification arguments if you chose to create a verification executable. Refer to the Intel High Level Synthesis Compiler User Guide for information on verification arguments.
  3. Click OK to compile the HLS file and create the component.
  4. If your HLS file defines more than one component, the Choose File to Import dialog box prompts you to select a specific component from a list.
  5. After compiling, click Show Report to display a compilation report in a browser window.
  6. If you created simulation files for your component, you can click Run Verification to perform verification.